Design Verification (DV) Engineer with PCIe

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

### Role & Company / Project Overview Mergen is hiring a Design Verification (DV) Engineer with PCIe expertise for its semiconductor verification operations in Hyderabad. ### Key Responsibilities & Daily Duties • Develop UVM/SystemVerilog testbenches and verification environments for PCIe IP and subsystems. • Write and execute test plans, functional assertions, and code/functional coverage metrics. • Debug RTL regressions and collaborate with microarchitecture and design engineers to resolve bugs. ### Required Qualifications, Skills & Experience • 5 to 10 years of experience in Design Verification. • Deep hands-on experience with PCIe protocol verification (Gen3/Gen4/Gen5). • Strong expertise in SystemVerilog, UVM, and assertion-based verification. ### Working Hours, Shifts & Location Details • Location: Hyderabad, Telangana, India. • Full-time engineering role. ### Application Instructions • Send updated resumes via email.