Functional Verification Engineer

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

### Role & Company / Project Overview Mergen is seeking an experienced Functional Verification Engineer in Hyderabad to drive verification efforts for sophisticated semiconductor chips. ### Key Responsibilities & Daily Duties • Architect and implement robust verification testbenches using SystemVerilog and UVM. • Write feature extraction documents, test plans, and functional assertions. • Run simulations, debug RTL defects, and drive code and functional coverage closure. ### Required Qualifications, Skills & Experience • 5 to 10 years of experience in functional verification for ASIC/SoC designs. • Expertise in SystemVerilog, UVM, and assertion-based verification techniques. • Solid debugging skills and familiarity with standard EDA simulators. ### Working Hours, Shifts & Location Details • Location: Hyderabad, Telangana, India. • Full-time engineering role. ### Application Instructions • Send your updated resume via email.