Physical Design Engineer - Chennai
- Location
- Chennai, Tamil Nadu, India
- Salary
- Not specified
- Company
- Akash pawar
Job description
• Role & Company / Project Overview We are hiring a Physical Design Engineer to build the next generation of chips with cutting-edge technology and innovation. • Key Responsibilities & Daily Duties - Implement VLSI physical design, floor planning, clock tree synthesis (CTS), and place and route (P&R). - Handle timing closure and Static Timing Analysis (STA). - Perform power planning and power routing. - Execute Design Rule Checking (DRC) and Layout Versus Schematic (LVS). - Drive block-level and top-level design implementation. - Work independently without a predefined customer flow. - Mentor and collaborate with junior engineers. • Required Qualifications, Skills & Experience - Education: BE/ME or BTech/MTech in Electrical Engineering or a related field. - Total Experience: 5+ Years. - Mandatory Skills: VLSI Physical Design, Floor Planning, Clock Tree Synthesis (CTS), Place and Route (P&R), Timing Closure & Static Timing Analysis (STA), Power Planning & Power Routing, Design Rule Checking (DRC) & Layout Versus Schematic (LVS). - Hands-on expertise with Cadence Innovus and/or Tempus. - Proven experience with 14nm or smaller technology nodes. - Preferred Skills: Experience working independently without a predefined customer flow, block-level and top-level design implementation, strong problem-solving and communication skills, ability to mentor and collaborate with junior engineers. • Working Hours, Shifts & Location Details - Location: Chennai, Tamil Nadu, India. - Work Mode: Work From Office (WFO). - Shift Timing: 9:00 AM – 6:00 PM. - Notice Period: Immediate to 30 Days. • Compensation & Benefits - Not specified. • Application Instructions - Virtual interview mode consisting of 2 rounds. - Interested candidates should submit their updated resume along with current location, total experience, relevant Physical Design experience, and notice period to the recruiter email.