ASIC Design Verification Engineer
- Location
- Pan India
- Salary
- Not specified
- Company
- akash pawar
Job description
Role & Company / Project Overview: We are hiring for our client an experienced ASIC Design Verification Engineer in the ASIC / Semiconductor / Data Center Networking domain. Key Responsibilities & Daily Duties: • Define and implement IP/SoC verification plans and develop robust verification testbenches. • Develop functional tests based on verification plans and drive Design Verification closure using functional and code coverage metrics. • Build and enhance SystemVerilog / UVM-based verification environments. • Perform simulation-based functional, performance, and compliance testing. • Debug failures, perform root-cause analysis, and collaborate closely with RTL Design teams to resolve issues. • Leverage advanced verification methodologies including Formal Verification and Emulation to achieve high-confidence, bug-free designs. • Partner with ASIC Design, Software, Model, Emulation, and Post-Silicon Validation teams to enable first-pass silicon success. • Drive continuous improvements in verification methodologies, automation, tools, and flows. • Mentor engineers and contribute to verification strategy for highly complex ASIC projects. Required Qualifications, Skills & Experience: • Bachelor’s degree in Computer Science, Computer Engineering, or a related technical field (or equivalent practical experience). • 8+ years of relevant ASIC Design Verification experience. • Strong track record of delivering first-pass silicon success. • Must-Have Technical Skills: Verilog, SystemVerilog, UVM / OVM, C / C++, Python-based verification, IP / Sub-System / SoC level verification, RTL & Gate-Level Verification, Verification Planning & Closure, Functional & Code Coverage, Simulation & Debugging, Verification Infrastructure Development. • Networking / Data Center Experience: Experience in one or more of Ethernet, 400G MAC, RDMA / RoCE, TSO / LRO, Congestion Control, High-speed networking, Data Center ASICs, AI/ML & Networking silicon is highly valuable. • Critical Technical Notes: 1. Ethernet MAC verification, preferably RDMA knowledge. 2. PCIe verification at SoC levels, preferably good exposure to TL. Pure PL knowledge is not OK. Pure DLL will not be shortlisted. 3. SoC advanced verification, covering data path, UPF, performance verification etc. Working Hours, Shifts & Location Details: • Location: India. Application Instructions: • Interested candidates can send their updated CV as per instructions.