PD Clocking Engineer

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

### Role & Company / Project Overview MPower Elyte is hiring a PD Clocking Engineer on behalf of a client in Hyderabad. This onsite position is responsible for owning and driving Clocking & Physical Design (PnR) methodologies for complex SoC and ASIC designs. ### Key Responsibilities & Daily Duties • Own and execute CTS, clock skew/latency optimization, and timing closure across designs. • Execute and oversee Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification. • Develop and maintain PnR implementation flows and methodologies. • Drive timing correlation across Tile PnR, Full-Chip Timing, STA, and Signoff stages. • Optimize timing, congestion, power, and area (Quality of Results - QoR). • Collaborate actively with CAD, Timing, DFT, FCFP, and Design engineering teams. ### Required Qualifications, Skills & Experience • 3 to 5 years of relevant industry experience in Physical Design / Clocking. • Bachelor's or Master's degree (B.E. / B.Tech / M.E. / M.Tech) in Electrical Engineering, Electronics Engineering, or a related discipline. • Strong expertise in CTS, clock skew and latency optimization, and timing closure. • Hands-on proficiency with tools including Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk. • Strong scripting skills in Tcl, Python, and Shell. • Experience with advanced process nodes such as 5nm, 3nm, and below is a strong plus. ### Working Hours, Shifts & Location Details • Location: Hyderabad, Telangana, India • Work Mode: Onsite • Open Positions: 1 ### Application Instructions Eligible and interested candidates should share their updated profile directly for consideration.