CPU Design Verification (RISC-V) - Hyderabad

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

• Role & Company / Project Overview: Semiconductor / VLSI career opportunity at AdvLogics for an experienced CPU Design Verification Engineer focused on RISC-V processor verification in Hyderabad. • Key Responsibilities & Daily Duties: - Architect, build, and execute robust verification environments for RISC-V core and CPU subsystems. - Write directed and constrained-random test cases in SystemVerilog/UVM and C/assembly. - Run and analyze functional coverage, code coverage, and regression suites to ensure zero-defect silicon readiness. - Interface with architecture and RTL design teams to isolate, debug, and resolve design issues. • Required Qualifications, Skills & Experience: - Experience: 5+ years of verified industry experience in CPU verification, processor cores, or complex ASIC/SoC DV. - Strong expertise in RISC-V instruction set architecture (ISA), SystemVerilog, and UVM methodology. - Degree in Electrical, Electronics, Computer Engineering, or related discipline. • Working Hours, Shifts & Location Details: - Location: Hyderabad, Telangana, India. - Standard professional engineering working schedule. • Compensation & Benefits: - Competitive industry package (details not disclosed). • Application Instructions: - Interested candidates should submit their updated resume via email.