CPU Design Verification (RISC-V) - Bangalore
- Location
- Bangalore, Karnataka, India
- Salary
- Not specified
- Company
- Akash pawar
Job description
• Role & Company / Project Overview: Exciting Semiconductor / VLSI opportunity at AdvLogics for a CPU Design Verification Engineer specializing in RISC-V architecture in Bangalore. • Key Responsibilities & Daily Duties: - Build and maintain comprehensive UVM/SystemVerilog testbenches for RISC-V CPU cores, subsystems, and microarchitectures. - Develop test plans, functional tests, random test generators, and coverage models. - Perform regression analysis, debug hardware failures, identify microarchitectural bugs, and achieve 100% functional and code coverage closure. - Collaborate closely with microarchitecture and RTL design teams. • Required Qualifications, Skills & Experience: - Experience: Minimum of 5+ years of hands-on experience in CPU or complex SoC design verification. - Deep domain expertise in RISC-V architecture and microarchitecture verification. - Strong proficiency with SystemVerilog, UVM, assembly-level test writing, and modern simulation/verification EDA tools. • Working Hours, Shifts & Location Details: - Location: Bangalore, Karnataka, India. - Standard corporate engineering office hours. • Compensation & Benefits: - Not specified. • Application Instructions: - Please share your updated resume via email. Referrals are welcome.