VLSI DFT Lead - Chennai

Location

Chennai, Tamil Nadu, India

Salary

Not specified

Company

Akash pawar

Job description

• Role & Company / Project Overview mSPANd is hiring a VLSI DFT Lead to lead DFT activities on advanced silicon designs at their Chennai development center. • Key Responsibilities & Daily Duties - Lead and execute DFT technical strategies including Scan insertion, ATPG, MBIST, and JTAG implementations. - Conduct ATPG pattern, JTAG, and MBIST pattern simulations with timing and no timing. - Architect and maintain automation flows using scripting languages. - Guide technical decisions across silicon testability and collaborate closely with cross-functional semiconductor design teams. • Required Qualifications, Skills & Experience - Experience: 8 to 10 years in VLSI Design for Testability (DFT). - Qualification: B.E or B.Tech (ECE/EEE), M.E or M.Tech (VLSI). - Strong knowledge in Digital Design & Verilog HDL. - Strong knowledge and experience in DFT (Design for Testability): JTAG, ATPG, Scan, MBIST. - Extensive experience in ATPG Pattern / JTAG / MBIST pattern simulation with timing & no timing. - Programming skills: Perl / TCL / Python. - Solid working knowledge in Operating Systems: Unix, Linux. • Working Hours, Shifts & Location Details - Location: Chennai, Tamil Nadu, India. - Onsite engineering role. • Application Instructions - Send your resume to the recruitment team.