Senior SerDes / DDR Circuit Design Engineer

Location

Bangalore, Karnataka, India

Salary

Not specified

Company

Akash pawar

Job description

Role & Company / Project Overview: TEKsystems is hiring a Senior SerDes / DDR Circuit Design Engineer to join a high-performance silicon engineering team working on advanced technology nodes and next-generation PHY solutions. Key Responsibilities & Daily Duties: • Design and analyze high-speed SerDes and/or DDR circuits. • Work on advanced process technologies including FinFET nodes. • Perform circuit design, functional analysis, static timing analysis (STA), and electrical sign-off. • Evaluate process variation impacts on circuit performance. • Execute project deliverables using AMD design methodologies and tools. • Release PHY components to SoC teams. Required Qualifications, Skills & Experience: • 5-8 years of relevant semiconductor design experience. • Education: Bachelor's or Master's in Electronics, Electrical Engineering, or VLSI Engineering. • Strong understanding and design knowledge in the SerDes domain. • Strong understanding of STA (Static Timing Analysis) concepts. • Hands-on experience with Cadence Virtuoso. • Strong understanding of power-performance tradeoffs in high-speed designs. • Experience with circuit characterization, timing analysis, and design validation. • Knowledge of PHY architectures, timing closure, and high-speed interface design. • Preferred Background: Engineers from domains such as SerDes, DDR, PHY Design, PCIe, USB, MIPI, LVDS, High-Speed I/O, PLL/DLL, CTLE, CDR. • Good to Have: Timing Characterization. • Good to Have: EM-IR Analysis Concepts. Working Hours, Shifts & Location Details: • Location: Bangalore, Karnataka, India. • Work Mode: Onsite (5 Days/Week). • Shift: Regular. Application Instructions: Interested candidates or those referring suitable professionals are invited to share their updated resume with the recruitment team.