DFT Principal Engineer

Location

Santa Clara, California, United States

Salary

Not specified

Company

Akash pawar

Job description

• Role & Company / Project Overview We are looking for an experienced DFT Principal Engineer with strong hands-on expertise in Scan Insertion, ATPG, MBIST, and SoC test validation to join our semiconductor engineering team. This position is open only for USA-based consultants. • Key Responsibilities & Daily Duties - Perform Scan Insertion and ATPG Validation for SoC architectures. - Execute fault coverage analysis, coverage improvement, and Test Point Insertion. - Handle MBIST insertion and integration. - Conduct ATPG Gate-Level Simulation (GLS) debugging covering both Zero Delay and SDF. - Execute SSN Pattern Retargeting and comprehensive SoC GLS validation. - Deliver end-to-end test validation and ATPG coverage optimization across complex ASIC/SoC designs. • Required Qualifications, Skills & Experience - 8 to 12 years of relevant hands-on DFT engineering experience. - Extensive experience with Siemens Mentor Tessent Scan & TestKompress. - Hands-on expertise with Cadence Modus. - Deep understanding and application of Stuck-at & Transition (At-Speed) fault models. - Strong proficiency with Synopsys Fusion Compiler (FC) and Design Compiler (DC). - Proven experience utilizing Synopsys VCS, Verdi, TetraMAX, SpyGlass, and Cadence Xcelium. - Hands-on ASIC/SoC design-for-test background. - Experience working in an Intel environment is considered a plus. • Working Hours, Shifts & Location Details - Location: Santa Clara, California, United States. - Work Mode: Onsite from Day 1. • Application Instructions - Qualified USA-based consultants are invited to apply by submitting an updated resume.