Senior Timing and Clocking Characterization Engineer (DLL

Location

Mountain View, California, United States

Salary

Not specified

Company

Akash pawar

Job description

### Role & Company / Project Overview We are looking for an experienced Semiconductor Engineer with strong expertise in custom clocking circuit characterization, Liberty timing models, and Static Timing Analysis (STA). ### Key Responsibilities & Daily Duties • Characterize custom clocking circuits including DLLs, DCCs, DCDLs, Phase Interpolators and Clock Dividers. • Develop Liberty (.lib) timing models, including NLDM, CCS and LVF. • Perform transistor-level characterization and SPICE correlation across PVT corners. • Execute production STA using Synopsys PrimeTime or Cadence Tempus. • Develop and validate SDC constraints, including generated clocks and timing exceptions. • Support MMMC, OCV/AOCV/POCV analysis and physical design handoff. • Automate characterization and STA workflows using Python, Tcl or Perl. ### Required Qualifications, Skills & Experience • 7+ years of relevant semiconductor engineering experience. • Hands-on DLL / DCC / Delay Line characterization. • Liberty timing library characterization using Liberate, PrimeLib, SiliconSmart or equivalent. • Production STA experience with PrimeTime or Tempus. • SPICE simulation experience (HSPICE, Spectre or PrimeSim). • Strong understanding of PVT, MMMC and OCV. **Preferred Experience:** • DDR / LPDDR / HBM PHY or SerDes clocking. • FinFET technology and multiple silicon tapeouts. • Physical design exposure using Innovus, ICC2 or Fusion Compiler. • Professionals with experience across both custom clocking circuit characterization and digital timing signoff are particularly encouraged. ### Working Hours, Shifts & Location Details • Location: Mountain View, CA Area • Work Arrangement: Onsite / Hybrid ### Application Instructions Interested candidates, please connect and submit an updated resume to the contact provided.