Memory Layout (ML) Engineer - Hyderabad

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

• Role & Company / Project Overview: Kea Semiconductors is expanding its VLSI team and hiring talented Memory Layout (ML) Engineers to be based in Hyderabad. • Key Responsibilities & Daily Duties: - Execute end-to-end memory layout design adhering to strict physical design rules. - Perform complete physical verification including DRC, LVS, and extraction checks. - Work closely with memory circuit design teams to meet quality and tapeout deadlines. • Required Qualifications, Skills & Experience: - Minimum 2+ years of hands-on experience in Memory Layout (ML). - Strong understanding of deep sub-micron process technologies and layout techniques. - Hands-on experience with industry-standard EDA verification suites. • Working Hours, Shifts & Location Details: - Location: Hyderabad, Telangana, India. - Full-time employment. • Compensation & Benefits: - Industry-competitive salary and benefits in the VLSI industry. • Application Instructions: - Send your updated resume to the hiring email provided.