Design Verification / GLS Engineer

Location

Hyderabad, Telangana, India

Salary

Not specified

Company

Akash pawar

Job description

Role & Company / Project Overview: Purna Semiconductor is hiring a Design Verification / Gate-Level Simulation Engineer to join their engineering team in Hyderabad. Key Responsibilities & Daily Duties: • Develop, maintain, and execute functional verification testbenches using SystemVerilog and UVM methodology. • Perform gate-level simulation (GLS) and timing verification with SDF annotation. • Support simulation migration from VCS to Xcelium. • Apply low-power verification concepts during verification cycles. • Conduct functional and code coverage analysis to achieve closure. • Carry out simulation debugging and regression failure analysis. • Support verification environment bring-up and migration activities. Required Qualifications, Skills & Experience: • 3+ years of relevant experience in Design Verification and Gate-Level Simulation. • Minimum 3 GLS projects with hands-on experience. • Strong hands-on experience in SystemVerilog (SV) & UVM methodology. • Strong experience in Design Verification (DV) and Gate-Level Simulation (GLS). • Strong knowledge of Verilog & SystemVerilog. • Experience with simulation migration from VCS to Xcelium. • Good understanding of Low-Power Verification concepts. • Strong experience in functional verification, testbench development & execution. • Good understanding of timing concepts & SDF annotation. • Strong knowledge of functional & code coverage analysis. • Experience in simulation debugging and regression failure analysis. • Experience in verification environment bring-up & migration support. • Strong debugging and problem-solving skills. • Preferred Profile: Engineers with practical experience in GLS, DV, simulation/debugging, coverage analysis, and verification environment migration. Working Hours, Shifts & Location Details: • Location: Hyderabad, India. Application Instructions: • Interested candidates can share their updated CV.