Job Details
Location: Cupertino, California, United States
Salary: USD 60 / hour
Company: ApnaWorker
We are seeking an experienced Analog Layout Design Engineer for an onsite role in Cupertino, CA. The ideal candidate must have 7+ years of experience and expertise in layout IC, CMOS FinFET, Cadence, Mentor, and Synopsys tools, as well as CMOS drivers. This is a C2C opportunity for USC/GC holders at $60 per hour. Responsibilities include designing and optimizing analog layouts, collaborating with cross-functional teams, and ensuring high-quality chip designs.