Job Details
Location: California-wide, United States
Salary: Not specified
Company: ApnaWorker
We are seeking an experienced Analog Layout Design Engineer for an onsite opportunity in California. The ideal candidate will have at least 6 years of experience in analog layout design, with expertise in developing and leading complex IC layouts for high-speed applications using advanced CMOS FinFET technologies (7nm and below) at both block and chip levels. Proficiency in industry-standard EDA tools such as Cadence, Mentor, and Synopsys is required. Experience with high-performance analog/mixed-signal blocks including Transceivers, CMOS Drivers, High-Speed Data Converters, and PLLs is essential. Responsibilities encompass floor planning, block-level routing, top-level chip assembly, layer generation, thermal-aware layout design, and electro-migration considerations.