Analog Layout Engineer - CoreIC Technologies
- Location
- Bengaluru, Karnataka, India
- Salary
- Not specified
- Company
- Akash pawar
Job description
• Role & Company / Project Overview CoreIC Technologies is expanding its semiconductor and VLSI engineering team in Bengaluru and is actively hiring an Analog Layout Engineer. This role focuses on high-precision physical layout execution and verification for analog integrated circuits. • Key Responsibilities & Daily Duties - Execute full custom analog physical layout design for blocks including amplifiers, bandgaps, PLLs, ADCs/DACs, and power management circuits. - Perform physical verification checks including DRC, LVS, ERC, Antenna, and DFM compliance. - Mitigate physical effects including matching, parasitic extraction (PEX), electromigration (EM), IR drop, and cross-talk issues. - Collaborate closely with analog design engineers to optimize layout floorplans and achieve silicon target performance. • Required Qualifications, Skills & Experience - 3+ years of professional hands-on experience in analog IC physical layout design in advanced technology nodes. - In-depth proficiency with industry-standard EDA layout and physical verification tools (e.g., Cadence Virtuoso, Mentor Calibre). - Notice period requirement: 0 to 90 Days. • Working Hours, Shifts & Location Details - Location: Bengaluru, Karnataka, India. - Working schedule: Standard full-time engineering schedule. • Compensation & Benefits - Competitive remuneration in line with semiconductor industry benchmarks. • Application Instructions - Ready for your next VLSI opportunity? Send your updated CV to the designated recruitment email.