Design for Testability (DFT) Engineer - Fresher

Location

Bangalore, Karnataka, India

Salary

Not specified

Company

Akash pawar

Job description

### Role & Company / Project Overview Juntran Technologies is hiring passionate and trained VLSI freshers for Design for Testability (DFT) to start their career in the semiconductor industry and chip design in Bangalore. ### Key Responsibilities & Daily Duties - Work on Design for Testability (DFT) architecture and implementation for complex ASIC and semiconductor chips. - Apply VLSI trained concepts including scan insertion, ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test), and boundary scan. - Perform simulation, fault analysis, and test pattern validation. - Collaborate with core engineering and design teams to ensure test coverage and timing closure. ### Required Qualifications, Skills & Experience - Education: B.Tech graduates (2023 and earlier pass-outs). - Training: Completed formal VLSI training with focus on DFT concepts. - Good understanding of digital design, testability concepts, and semiconductor workflows. - Strong analytical and problem-solving skills. ### Working Hours, Shifts & Location Details - Location: Bangalore, Karnataka, India. - Joining Timeline: Immediate to 15 days. - Regular full-time engineering schedule. ### Application Instructions - Send your resume to the Juntran Technologies hiring team.