Job Details
Location: Bangalore, Karnataka, India
Salary: Not specified
Company: ApnaWorker
We are seeking a highly skilled Design Verification Engineer with strong expertise in Automotive SerDes, SystemVerilog, and UVM to join our team and contribute to next-generation high-speed automotive connectivity solutions. Key responsibilities include performing block-level and chip-level functional verification of ASA IP integration, ASA link datapath, and ASEP application streams; developing and maintaining UVM-based verification environments for ASA IP, ASEP application layer, and end-to-end CSI-2 to ASA link scenarios; creating and executing constrained-random test scenarios covering PHY power-up, TDD mode switching, light sleep modes, speed-grade transitions, IBG timing, and synchronization mechanisms; integrating and validating ASA IP simulation models (behavioral and gate-level) including PHY AMS/mixed-signal co-simulation; developing protocol checkers for ASA-ML DLL containers, ASEP framing, OAM transactions, CRC validation, and LLS security frames; and driving regression management, functional and code coverage closure, and formal CDC/reset verification. Required skills include strong experience in SystemVerilog and UVM, hands-on experience with Cadence Xcelium and vManager, expertise in functional verification, protocol verification, coverage closure, and regression management, and experience with CDC/reset verification and formal verification methodologies. The role requires prior experience in Automotive SerDes Design Verification, with exposure to ASA, ASEP, CSI-2, or related automotive communication protocols highly preferred.